In many electronic devices (e.g. high-definition televisions (HD-TVs), high-definition video cassette recorders (HD-VCRs), digital VCRs, digital camcorders, and multimedia systems), both a video signal and an audio signal are digitally processed, and the processed signals are recorded on a recording medium or transmitted to another reproducing apparatus. Several methods for digitally processing the video information include a prediction coding method, an orthogonal transform coding method, and a variable length coding method. In order to execute the methods above, typical coding systems perform an orthogonal transform coding operation, a quantization operation, and a variable length coding operation. Furthermore, such operations are performed on a predetermined portion (i.e. block) of the video signal in order to effectively compress video information. Moreover, such systems perform a prediction coding operation between frames or fields of the video information in order to further enhance the data compression rate.
The above-described variable length coding apparatuses compress information based on symbols contained within the video information, and a variable length code table is stored for coding the input symbols. In particular, the variable length coding table is created according to the well known Huffman coding technique. According to such technique, shorter codes are assigned to symbols which occur more frequently, and longer codes are assigned to symbols which occur less infrequently.
In a typical coding system, symbols which are input to a variable length coding apparatus are [run, level] symbols that are generated based on a run-length coding operation. For example, the [run, level] symbols may be obtained in accordance with a well-known zig-zag scan. Specifically, the "run" represents the number of "0"s which sequentially exist between non-zero transform coefficients obtained by the zig-zag scan, and the "level" represents a value of the non-zero transform coefficient.
In addition to being created based on the Huffman coding technique, the table may be divided into an escape region and a regular region. In particular, the escape region contains codes in which either the "run" or "level" has a large value, and the regular region represents all of the other situations. The [run, level] symbols located in the regular region are assigned codes according to the Huffman coding technique. On the other hand, the [run, level] symbols in the escape region are assigned and escape (ESC) code and a longer code since the [run, level] symbols in the escape region occur infrequently. Based on the data in the code table, the [run, level] symbols are converted into a bitstream of data in which additional information such as the ESC code and an end of block (EOB) code representing the end of a block of data is added. Subsequently, the bitstream of data is transmitted to a decoding system.
The decoding system performs a decoding operation which is the inverse of the signal processing operation of the coding system. Specifically, the decoding system comprises a variable length decoder, an inverse quantizer, and an inverse orthogonal transformer to decode the coded information.
A conventional variable length decoder is illustrated in FIG. 1. As illustrated in the figure, the conventional decoder comprises a barrel shifter 11 and a Read Only Memory (ROM) 15. The barrel shifter 11 inputs a bitstream of data and outputs certain data bits to the ROM 15 as address data ADDR. Then, the ROM 15 reads the [run, level] symbols stored at the address location designated by the address data ADDR and outputs the [run, level] symbols to the inverse quantizer (not shown).
Furthermore, the ROM 15 generates a code length symbol based on the output [run, level] symbol and supplies the code length symbol to the barrel shifter 11. Subsequently, the barrel shifter 11 outputs another predetermined set of data bits as the address data ADDR based on the code length signal. The barrel shifter 11 and the ROM 15 repeat the operations above to continuously perform the variable length decoding operation.
Since the apparatus illustrated in FIG. 1 can generate a single [run, level] symbol with a single shift operation and a single reading operation (usually two clock pulse periods) regardless of the code length of the [run, level] symbols, the apparatus can consistently operate at a constant speed and can operate at a high frequency. However, the variable length decoding apparatus requires a ROM 15 for storing the variable length coding table and a barrel shifter 11 for generating address data ADDR for the ROM 15. Thus, when such a variable length decoding apparatus is manufactured as an application specific integrated circuit (ASIC), the complexity of the hardware and the cost of the apparatus increases.